The telecommunications industry, through the European Broadcasting Union, has promulgated a set of standards for digital video broadcasting (DVB). Among the most recent of such standards is one (entitled ETSI EN 302 304, “Digital Video Broadcasting Transmission System for Handheld Terminals”) related to digital video broadcasting (DVB) to a handheld device (DVB-H), which sets forth agreed upon requirements for delivering live broadcast television to mobile phones and the like. In large part, this standard relies upon earlier-developed standards within the DVB family, including ETSI EN 301 192, “Digital Video Broadcasting Specification for Data Broadcasting”. Each of these documents is incorporated herein by reference.
With DVB-H, viewers are able to receive television-like services on their handheld devices. While exciting, this prospect does pose certain technical challenges for example with respect to power consumption at the handheld device. In order to prolong battery life of a handheld device, the DVB-H specification provides for “time-saving”. That is, data is delivered to the handheld device in bursts at various time intervals. When not receiving a desired burst of data, the tuner of the handheld device is powered down, thereby conserving battery power. The user does not notice the period of inactivity since the data bursts are stored in memory and played out continuously.
It is anticipated that a typical user of a battery-operated television receiver that is incorporated into a device such as a cellular telephone will desire one or two hours of television function per day, in addition to any telephone talk time, before recharging the device at the end of the day. Existing integrated circuit chips for demodulating digital DVB signals according to the standards promulgated by the European Telecommunications Standards Institute (ETSI), consume too much power to allow the anticipated use time without requiring unacceptably large batteries. Consequently, various methods have been used or proposed to reduce power consumption. For example, chip designers have sought to reduce power consumption by scaling down feature dimensions, which results in reduced internal (parasitic) capacitance, and by reducing the chip's operating voltage. Other methods focus on powering down through clock gating of components or portions of a chip that are not being used.
Luca Benini et al., Monitoring System Activity for OS-Directed Dynamic Power Management, Power Electronics and Design, 1998 Proceedings, pp. 185-190, 1998 ACM 1-58113-059-7/98/0008, purports to disclose a data collection tool for collecting and analyzing data that is relevant for dynamic power management, and discusses dynamic power management methods aimed at putting system components into a low power sleep mode when they are idle. Masakatsu Nakai et al., Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor, IEEE Journal of Solid-State Circuits, Vol. 40, Issue 1 (January 2005), pp. 28-35, purports to disclose a dynamic voltage and frequency management technique in which the supply voltage is varied, and the clock frequency of a processor is varied according to the level of system activity detected.